96 research outputs found

    Hierarchical Scheduling for Real-Time Periodic Tasks in Symmetric Multiprocessing

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    In this paper, we present a new hierarchical scheduling framework for periodic tasks in symmetric multiprocessor (SMP) platforms. Partitioned and global scheduling are the two main approaches used by SMP based systems where global scheduling is recommended for overall performance and partitioned scheduling is recommended for hard real-time performance. Our approach combines both the global and partitioned approaches of traditional SMP-based schedulers to provide hard real-time performance guarantees for critical tasks and improved response times for soft real-time tasks. Implemented as part of VxWorks, the results are confirmed using a real-time benchmark application, where response times were improved for soft real-time tasks while still providing hard real-time performance

    Clock Gating Flip-Flop using Embedded XoR Circuitry

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    Flip flops/Pulsed latches are one of the main contributors of dynamic power consumption. In this paper, a novel flip-flop (FF) using clock gating circuitry with embedded XOR, GEMFF, is proposed. Using post layout simulation with 45nm technology, GEMFF outperforms prior state-of-the-art flip-flop by 25.1% at 10% data switching activity in terms of power consumption

    Fast Adjustable NPN Classification Using Generalized Symmetries

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    NPN classification of Boolean functions is a powerful technique used in many logic synthesis and technology mapping tools in FPGA design flows. Computing the canonical form of a function is the most common approach of Boolean function classification. In this paper, a novel algorithm for computing NPN canonical form is proposed. By exploiting symmetries under different phase assignments and higher-order symmetries of Boolean functions, the search space of NPN canonical form computation is pruned and the runtime is dramatically reduced. The algorithm can be adjusted to be a slow exact algorithm or a fast heuristic algorithm with lower quality. For exact classification, the proposed algorithm achieves a 30× speedup compared to a state-of-the-art algorithm. For heuristic classification, the proposed algorithm has similar performance as the state-of-the-art algorithm with a possibility to trade runtime for quality

    Towards QoS-Based Embedded Machine Learning

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    Due to various breakthroughs and advancements in machine learning and computer architectures, machine learning models are beginning to proliferate through embedded platforms. Some of these machine learning models cover a range of applications including computer vision, speech recognition, healthcare efficiency, industrial IoT, robotics and many more. However, there is a critical limitation in implementing ML algorithms efficiently on embedded platforms: the computational and memory expense of many machine learning models can make them unsuitable in resource-constrained environments. Therefore, to efficiently implement these memory-intensive and computationally expensive algorithms in an embedded computing environment, innovative resource management techniques are required at the hardware, software and system levels. To this end, we present a novel quality-of-service based resource allocation scheme that uses feedback control to adjust compute resources dynamically to cope with the varying and unpredictable workloads of ML applications while still maintaining an acceptable level of service to the user. To evaluate the feasibility of our approach we implemented a feedback control scheduling simulator that was used to analyze our framework under various simulated workloads. We also implemented our framework as a Linux kernel module running on a virtual machine as well as a Raspberry Pi 4 single board computer. Results illustrate that our approach was able to maintain a sufficient level of service without overloading the processor as well as providing an energy savings of almost 20% as compared to the native resource management in Linux

    Investigating on Through Glass via Based RF Passives for 3-D Integration

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    Due to low dielectric loss and low cost, glass is developed as a promising material for advanced interposers in 2.5-D and 3-D integration. In this paper, through glass vias (TGVs) are used to implement inductors for minimal footprint and large quality factor. Based on the proposed physical structure, the impact of various process and design parameters on the electrical characteristics of TGV inductors is investigated with 3-D electromagnetic simulator HFSS. It is observed that TGV inductors have identical inductance and larger quality factor in comparison with their through silicon via counterparts. Using TGV inductors and parallel plate capacitors, a compact 3-D band-pass filter (BPF) is designed and analyzed. Compared with some reported BPFs, the proposed TGV-based circuit has an ultra-compact size and excellent filtering performance

    Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicron CMOS Circuits

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    As the devices are scaling down, the combinational logic will become susceptible to soft errors. The conventional soft error tolerant methods for soft errors on combinational logic do not provide enough high soft error tolerant capability with reasonably small performance penalty. This paper investigates the feasibility of designing quasi-delay insensitive (QDI) asynchronous circuits for high soft error tolerance. We analyze the behavior of null convention logic (NCL) circuits in the presence of particle strikes, and propose an asynchronous pipeline for soft-error correction and a novel technique to improve the robustness of threshold gates, which are basic components in NCL, against particle strikes by using Schmitt trigger circuit and resizing the feedback transistor. Experimental results show that the proposed threshold gates do not generate soft errors under the strike of a particle within a certain energy range if a proper transistor size is applied. The penalties, such as delay and power consumption, are also presented

    Binary Nonlinearization for AKNS-KN Coupling System

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    The AKNS-KN coupling system is obtained on the base of zero curvature equation by enlarging the spectral equation. Under the Bargmann symmetry constraint, the AKNS-KN coupling system is decomposed into two integrable Hamiltonian systems with the corresponding variables x, tn and the finite dimensional Hamiltonian systems are Liouville integrable

    Invariant Solutions and Conservation Laws of the (2 + 1)-Dimensional Boussinesq Equation

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    Invariant solutions and conservation laws of the (2 + 1)-dimensional Boussinesq equation are studied. The Lie symmetry approach is used to obtain the invariant solutions. Conservation laws for the underlying equation are derived by utilizing the new conservation theorem and the partial Lagrange approach
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